The present invention relates to a semiconductor device, an electric equipment, a bidirectional field effect transistor, and amounted structure body and, more particularly to a semiconductor device using a gallium nitride (GaN)-based semiconductor, an electric equipment using the semiconductor device, a bidirectional field effect transistor, an electric equipment using the bidirectional field effect transistor, and a mounted structure body comprising the semiconductor device or the bidirectional field effect transistor.
With increasing the importance of electric energy to realize energy saving society, in the twenty first-century, it is going to rely on electric power further. The key devices of electric and electronic equipments are semiconductor devices such as transistors and diodes. Therefore, energy saving characteristic of these semiconductor devices is very important. At present, a silicon (Si) semiconductor device is used as a power conversion device, but the silicon semiconductor device has been improved its performance to the limit of physical properties. Therefore, it is under difficult situation to save energy further.
For this, the research and development has been carried out intensively on the power conversion devices with a wide-gap semiconductor such as silicon carbide (SiC) and gallium nitride (GaN) in place of Si. Among them, GaN has remarkably better physical properties in power efficiency and voltage-resistance property than SiC. Therefore, the research and development for GaN-based semiconductor devices has been carried out energetically.
With regard to the GaN-based semiconductor device, a lateral type field effect transistor (FET), that is, a device with a structure formed with a transporting channel parallel to a substrate has been developed. For example, such a device is a device wherein upon a base substrate made of sapphire, SiC, etc., an undoped GaN layer is stacked with a few-μm-thick, and on it, an AlGaN layer with an Al composition of about 25% is stacked with about 25 to 30-nm-thick, and a two-dimensional electron gas (2DEG) formed at an AlGaN/GaN hetero-interface is used. The device is generally called a HFET (hetero-junction FET).
The AlGaN/GaN HFET has a technical problem of control of current collapse. The phenomenon of current collapse is a phenomenon that for the drain current at a low drain voltage up to several volts, the drain current after a high voltage is applied decreases. The phenomenon means in real circuits a phenomenon that the drain current at an on time decreases when an operation voltage of switching becomes high. The current collapse is not a unique phenomenon in a GaN-based FET, but comes to appear remarkably with enabling to apply a high voltage between a source and a drain in the GaN-based FET, and is originally a phenomenon generally arising in horizontal type devices.
The cause of generation of current collapse is explained as follows. When a high voltage is applied between a gate and a drain of a FET, or between a cathode and an anode of a diode, a high electric field area is generated just below the gate or just below the anode, and electrons transfer to the surface or surface vicinity of a part of the high electric field to be trapped. The source of electrons is electrons which drift on the surface of a semiconductor from a gate electrode, or channel electrons which transfer to the surface by a high electric field, etc. By being biased to negative by the negative charges of the electrons, the electron concentration of the electronic channel decreases and the channel resistance goes up.
With regard to electrons generated by gate leakage, by making passivation by the dielectric film on the surface, electron transfer is limited and the current collapse is controlled. However, current collapse cannot be sufficiently controlled only by the dielectric film.
Therefore, focusing on that the current collapse results from a high electric field in the vicinity of a gate, a technology to control the intensity of electric field, especially peak electric field, has been developed. This is called the Field Plate (FP) technology, which is the heretofore known technology already in practical use in a Si-based or a GaAs-based FET (for example, see non-patent literature 1.).
FIG. 1A shows a conventional AlGaN/GaN HFET using the field plate technology. As shown in FIG. 1A, with regard to the AlGaN/GaN HFET, on a base substrate 101, a GaN layer 102 and an AlGaN layer 103 are stacked in order, and on the AlGaN layer 103, a gate electrode 104, a source electrode 105, and a drain electrode 106 are formed. In this case, the upper part of the gate electrode 104 and the upper part of the source electrode 105 extend to the side of the drain electrode 106 like a hat brim, and form field plates. By the field plates formed to the gate electrode 104 and the source electrode 105, based on the principle of electromagnetism, the peak electric field intensity of the end of a depletion layer of a channel can be lowered. FIG. 1B shows the electric field distribution of cases with and without field plates corresponding to FIG. 1A. As the area of electric field distribution is equal to a drain voltage, by dispersing the peak electric field, the improvement of voltage resistance of the AlGaN/GaN HFET and a control of current collapse can be made.
However, by the field plate technology, the electric field cannot be leveled over all the channel area. Also, a practical semiconductor device as a power device is applied a voltage of 600 V or more, therefore, the issue cannot be fundamentally solved even if the field plate technology is applied.
On the other hand, there is a super junction structure, one of the heretofore known technologies, which improves voltage resistance by equalizing the electric field distribution, and making the peak electric field unlikely occur (for example, see non-patent literature 2.). The super junction is explained.
FIG. 2A shows a conventional pn junction applied a small reverse bias voltage. FIG. 3A shows a unit of a super junction applied a small reverse bias voltage.
As shown in FIG. 2A, in the conventional pn junction, a p-type layer 151 and an n-type layer 152 are joined, a p-electrode 153 is formed on the p-type layer 151, an n-electrode 154 is formed on the n-type layer 152, and the junction plane of the pn junction is parallel to the p-electrode 153 and the n-electrode 154. In the vicinity part of the junction plane of the p-type layer 151, a depletion layer 151a is formed, and the other part is a p-type neutral region. On the vicinity part of the junction plane of the n-type layer 152, a depletion layer 152a is formed, and the other part is an n-type neutral region.
In contrast with this, as shown in FIG. 3A, in the super junction, a pn junction is formed by a p-type layer 201 and an n-type layer 202 as the same as the conventional pn junction, but a p-electrode 203 formed on the p-type layer 201 and an n-electrode 204 formed on the n-type layer 202 are formed such that they intersect at right angle for the main junction plane stretching in a plane between the p-type layer 201 and the n-type layer 202. At the both end parts of the pn junction, the junction plane is curved to the opposite direction each other for the main junction plane. In the vicinity part of the junction plane of the p-type layer 201, a depletion layer 201a is formed, and the other part is a p-type neutral region. In the vicinity part of the junction plane of the n-type layer 202, a depletion layer 202a is formed, and the other part is an n-type neutral region.
FIG. 2B shows the electric field distribution of the conventional pn junction applied a small reverse bias voltage between the p-electrode 153 and the n-electrode 154 corresponding to FIG. 2A. Also, FIG. 3B shows the electric field distribution of the super junction applied a small reverse bias voltage between the p-electrode 203 and the n-electrode 204 corresponding to FIG. 3A.
FIG. 4A shows that a large reverse bias voltage is applied to the conventional pn junction. FIG. 5A shows that a large reverse bias voltage is applied to the super junction.
FIG. 4B shows the electric field distribution of the conventional pn junction applied a large reverse bias voltage between the p-electrode 153 and the n-electrode 154 corresponding to FIG. 4A. Also, FIG. 5B shows the electric field distribution of the super junction applied a large reverse bias voltage between the p-electrode 203 and the n-electrode 204 corresponding to FIG. 5A.
In the conventional pn junction and the super junction, the expansion of the depletion layers 151a, 152a, 201a, and 202a occurs starting at the pn junction plane. In the conventional pn junction, the electric field distribution by fixed charge of acceptor ions, donor ions, etc. in the depletion layers 151a, 152a becomes triangle shape as shown in FIG. 2B and FIG. 4B, and the peak electric field distribution occurs. In contrast with this, in the super junction, as shown in FIG. 3B and FIG. 5B, when the depletion layers 201a, 202a expand, the electric field (value of integral of charge) distributes with a constant value in the direction connecting between the p-electrode 203 and the n-electrode 204, and it is understood that concentration of electric field does not occur.
As the applied voltage is the value of integral of electric field (corresponding to the area of electric field in FIG. 2B, FIG. 3B, FIG. 4B, and FIG. 5B), in the conventional pn junction, the voltage resistance is controlled by the maximum electric field intensity occurring at the junction plane. On the other hand, the super junction can withstand the applied voltage over the whole semiconductor with homogeneous electric field. The super junction is applied to a drift layer of a Si-MOS power transistor and a Si power diode with a vertical type or a horizontal type structure.
Also, there is the principle of polarization junction as a method to produce distribution of positive charge and negative charge as the same as the super junction without depending on the pn junction (for example, see patent literature 1.). Also, there is proposed a technology aiming high voltage resistance by making use of the polarization (for example, see patent literature 2.).
However, it is proved that the two-dimensional hole concentration of the polarization junction described in the patent literatures 1 and 2 is insufficient for high performance operation. Its reason is as follows. Negative polarization electric charge at the hetero-interface resulting the two-dimensional hole at the hetero-interface is compensated by surface defects or surface levels. As a result, the band is pushed downwardly, resulting the reduction of the concentration of the two-dimensional hole to be present at the AlGaN/GaN hetero-interface.
Therefore, a semiconductor device that can improve the problem of the polarization junction described in the patent literatures 1 and 2 was proposed (see patent literature 3 and non-patent literature 3.). The semiconductor device has a structure in which an InzGa1-zN layer (where 0≤z<1), an AlxGa1-xN layer (where 0<x<1), an InyGa1-yN layer (where 0≤y<1) and a p-type InwGa1-wN layer (where 0≤w<1) are stacked in order. In the semiconductor device, a two-dimensional hole gas is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-yN layer and the InyGa1-yN layer, and a two-dimensional electron gas is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer at a non-operating time. More specifically, according to the semiconductor device, for example, the surface GaN layer is doped with Mg, and the band near the surface is lifted up by negative fixed electric charge of Mg acceptors, so that a sufficient two-dimensional hole gas is formed in the AlGaN/GaN hetero-interface on the surface side. And a transistor utilizing essentially the polarization effect was published for the first time (see non-patent literature 4.).